DO-254 AXI 7-Series DDRx (Limited) 1.01a

The DO-254 AXI 7-Series DDRx (Limited) 1.01a uses the Xilinx^®-7 Series FPGAs memory interface solutions to provide high-performance connections to DDR3 and DDR2 SDRAMs. Xilinx^®-7 Series FPGAs memory interface solutions core is a combined pre-engineered controller and physical layer (PHY) for interfacing 7 series FPGA user designs and AMBA^® advanced extensible interface (AXI4) slave interfaces to DDR3 and DDR2 SDRAM devices. In the Embedded Development Kit (EDK), this core is provided through the Xilinx^® Platform Studio (XPS) as the DO-254 AXI 7-Series DDRx (Limited) 1.01a IP located in the DO-254 IP library with a static AXI4 to DDR3 or DDR2 SDRAM architecture.

The DO-254 AXI 7-Series DDRx (Limited) 1.01a interface supports operation with the Xilinx^® MicroBlaze™ processor. The DO-254 AXI 7-Series DDRx (Limited) 1.01a interface maps AXI4 transactions coming from the MicroBlaze™ to the User Interface Block providing an industry-standard bus protocol interface to the memory controller. It enables the MicroBlaze™ to use external SDRAMs through the AXI4 interface, thereby increasing its versatility.

Key features are:

DDR3 SDRAM Features

Component support for interface widths up to 64 bits
Single rank UDIMM and SODIMM support
DDR3 (1.5 V) and DDR3L (1.35 V)
1, 2, and 4 Gb density device support
8-bank support
x8 and x16 device support
8:1 DQ:DQS ratio support
Configurable data bus widths (multiples of 8, up to 64 bits)
8-word burst support
Support for 5 to 11 cycles of column-address strobe (CAS) latency (CL)
On-die termination (ODT) support
Support for 5 to 8 cycles of CAS write latency
Write leveling support for DDR3 (fly-by routing topology required for DDR3 component designs)
JEDEC-compliant DDR3 initialization support
Source code written in Verilog
4:1 and 2:1 memory to FPGA logic interface clock ratio
Internal VREF support
Multicontroller support for up to eight controllers
Two controller request processing modes:
- Normal: Reorder requests to optimize system throughput and latency
- Strict: Memory requests are processed in the order received

DDR2 SDRAM Features

Component support for interface widths up to 64 bits
Single rank UDIMM and SODIMM
1 and 2 Gb density device support (additional densities supported in the MIG tool using the Create Custom Part feature)
4- and 8-bank support
x8 and x16 device support
8:1 DQ:DQS ratio support
Configurable data bus widths (multiples of 8, up to 64 bits)
8-word burst support
Support for 4 to 5 cycles of column address strobe (CAS) latency
On-die termination (ODT) support
JEDEC-compliant DDR2 initialization support
Source code written in Verilog
4:2 and 2:1 memory to FPGA logic interface clock ratio
Internal VREF support
Two controller request processing modes:
- Normal: Reorder requests to optimize system throughput and latency
- Strict: Memory requests are processed in the order received

Documentation

The COTS version v1.03a is the baseline from which the DO-254 AXI 7-Series DDRx (Limited) 1.01a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 AXI 7-Series DDRx (Limited) 1.01a. Below are links to the Xilinx^®Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx^® Product Specification:

http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v1_8/ds176_7Series_MIS.pdf

Link to the Logicircuit Data Sheet:

DO-254 AXI 7-Series DDRx (Limited) 1.01a Data Sheet