The Advanced eXtensible Interface ( AXI) External Memory Controller (EMC) provides the control interface for external synchronous, asynchronous SRAM, Flash and PSRAM/Cellular RAM memory devices through the AXI interface. This soft IP core is designed to interface with the AXI4 interface.
Key features are:
- Supports AXI4 specification for AXI interface
- Full AXI4 slave interface supports 32-bit address bus and 32/64-bit data bus
- Supports 32-bit configurable AXI4-Lite control interface to access internal registers
- Supports Burst transfers of 1-256 beats for INCR burst type and 2, 4, 8, 16 beats for WRAP burst type
- Supports AXI narrow transfers, unaligned transfer type of transactions
- Supports multiple (up to 4) external memory banks
- Supports independent memory configuration of each memory bank
- Supports memory data widths of 64-bit, 32-bit, 16-bit and 8-bit for each of the memory banks
The COTS version v1.03a is the baseline from which the DO-254 AXI External Memory Controller (EMC)1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 AXI External Memory Controller (EMC)1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Specification:
Link to the Logicircuit Data Sheet:
Device Family Support