The AXI Lite IPIF provides a point-to-point bi-directional interface between a user IP core and the AXI interconnect. This version of the AXI4-Lite IP Interface (IPIF) has been optimized for slave operation on the AXI. It does not provide support for DMA and IP Master Services.
Key features are:
- Supports 32-bit slave configuration
- Supports read and write data transfers of 32-bit width
- Supports multiple address ranges
- If there is a simultaneous read/write on AXI, read has the higher priority over write
- Reads to the holes in the address space returns 0x00000000
- Writes to the holes in the address space after the register map are ignored and responded with an OKAY response.
- IPIF will not perform endian conversion. Both AXI and IP Interconnect (IPIC) are little endian.
The COTS version v1.01.a is the baseline from which the DO-254 AXI4-Lite IP Interface (IPIF) 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 AXI4-Lite IP Interface (IPIF) 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link ot the Xilinx® Product Specification:
Link to the Logicircuit Data Sheet:
Device Family Support