DO-254 FIFO Generator 1.00a

The LogiCORE™ IP FIFO Generator core generates fully verified first-in, first-out (FIFO) memory queues ideal for applications requiring in-order data storage and retrieval.

The parameterized core is optimized to deliver maximum performance (up to 500 MHz) with minimal resource utilization. Flexible feature set allows users to customize for Memory type, Data width, FIFO depth, Flags, Aspect ratios and First Word Fall Through (FWFT) features.

Starting in ISE Design Suite release12.3, the following AXI4 interface options are also supported: AXI4 (memory mapped), AXI4-Stream and AXI4-Lite.

A Migration Guide is available to provide guidance on how to migrate existing designs to latest version of the core.

Key features are:

  • FIFO depths up to 4,194,304 words
  • FIFO data widths from 1 to 1024 bits for Native FIFO configurations and up to 4096 bits for AXI FIFO configurations
  • Non-symmetric aspect ratios (read-to-write port ratios ranging from 1:8 to 8:1)
  • Supports Independent or common clock domains
  • Selectable memory type (Block RAM, Distributed RAM, Shift Register, or Built-in FIFO)
  • Native or AXI interface (AXI4, AXI4-Lite, or AXI4-Stream)
  • Synchronous or asynchronous reset option
  • Supports Packet Mode
  • Supports Error Correction (ECC) and Injection feature for certain configurations
  • Supports First-Word Fall-Through (FWFT)
  • Supports Embedded Register option for Block RAM and Built-in FIFO primitive based implementations
  • Supports – Empty/Full, Almost Empty/Full, and Programmable Empty/Full signals

 

Documentation

The COTS version v9.3 is the baseline from which the DO-254 FIFO Generator 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 FIFO Generator 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx® Product Guide:

http://www.xilinx.com/support/documentation/ip_documentation/fifo_generator/v9_3/pg057-fifo-generator.pdf

Link to the Logicircuit Data Sheet:

DO-254 FIFO Generator 1.00a Data Sheet

 

Device Family Support

Xilinx® Artix-7

Xilinx® Kintex-7

Xilinx® Virtex-7

Xilinx® Zynq-7000

Xilinx® Spartan®-6