DO-254 Integrated Block for PCIe 1.10a

The PCI Express (PCIe) IP core is a high-performance, highly flexible, scalable, and reliable, general-purpose I/O core. The PCIe IP core is a scalable, high-bandwidth, and reliable serial interconnect building block for use with all Xilinx® 7 series Field Programmable Gate Arrays (FPGAs) families. This core incorporates Xilinx® Smart-IP technology to guarantee critical timing. The DO-254 PCIe IP core will support up to 2-lane Endpoint configurations at up to 5 Gb/s speeds.  The core includes other non-programmable features such as 8B/10B encode and decode, as well as supports a maximum transaction payload of up to 128 byte.

Key features are:

  • Compliant with PCI Express Base Specification, rev. 2.1
  • 1 lane or 2 lane operation
  • Support for shared clocking (external MMCM)
  • Supports lane reversal and lane polarity inversion
  • AXI-Stream user interface
  • Custom Vendor ID
  • Custom Device ID
  • Custom Revision ID
  • Custom Subsystem Vendor ID
  • Custom Subsystem ID
  • Supports 1 or 2 BARs (both customizable sizes)
  • Configurable acceptable latency
  • Supports enabling/disabling Virtual Channels

Documentation

The COTS version v3.3 is the baseline from which the DO-254 PCI Express (PCIe) IP core 1.10a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 PCI Express (PCIe) 1.10a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx® Product Guide:

7 Series FPGAs Integrated Block for PCI Express v3.3

Link to the Logicircuit Data Sheet:

< Unavailable at the moment >

Core Configurations

Core Version Features Tool Capability
1.00a
  • 1 lane or 2 lane operation
  • Supports a maximum transaction payload of up to 128 byte
  • Configuration Interface signals with the following exceptions:
    • cfg_command bit 2 (Bus Master Enable)
    • cfg_trn_pending
    • cfg_bus_number
    • cfg_device_number
    • cfg_err_ur
    • cfg_err_cpl_rdy
 ModelSim® v10.4 or later

Xilinx® Vivado® 2016.1 or later
1.10a
  • 1 lane or 2 lane operation
  • Supports a maximum transaction payload of up to 128 byte
  • Configuration Interface signals with the following exceptions:
    • cfg_command bit 2 (Bus Master Enable)
    • cfg_trn_pending
    • cfg_bus_number
    • cfg_device_number
    • cfg_err_ur
    • cfg_err_cpl_rdy
 ModelSim® v10.4 or later

Xilinx® Vivado® 2016.1 or later

Tools

ModelSim® v10.4 or later

Xilinx® Vivado® 2016.1 or later

Device Family Support

Xilinx® Artix™-7

Xilinx® Kintex™-7

Xilinx® Virtex™-7

Xilinx® Zynq™-7