The Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification. The core utilizes device primitives such as Virtex™-7 ICAP and ECC blocks to clock and observe the readback CRC circuit as part of the SEU detection function. For SEU correction, the IP core performs the necessary operations to locate and correct SEU errors using the Virtex™-6 built-in ECC facility. For SEU classification, the IP core uses Xilinx Essential Bits technology to further increase system reliability.
The SEM IP core also performs emulation of SEUs within 7-Series, Virtex™-6 and Spartan®-6 devices by injecting errors into the configuration memory. The error injection feature provides a means to evaluate and test the readback CRC circuit and the error correction capabilities of the IP core which is impossible with real SEUs.
Key features are:
- Automatically detects, corrects, and classifies SEU errors
- Supports error injection so all aspects of a system can be evaluated
- Supports up to 100 MHz clock.
- Functions as “Intelligent Sensor” that connects to the system
- Includes simple UART interface to connect to either a terminal or embedded processor
- Supports VHDL and Verilog
The COTS version v3.4 is the baseline from which the DO-254 Soft Error Mitigation Controller 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 Soft Error Mitigation Controller 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Guide:
Link to the Logicircuit Data Sheet:
Device Family Support