DO-254 7-Series DDRx (Native-Limited) 1.00a

The DO-254 7-Series DDRx (Native-Limited) 1.00a uses the Xilinx^®-7 Series FPGAs memory interface solutions core is a combined pre-engineered controller and physical layer (PHY) for interfacing 7 series FPGA user designs and native interfaces to DDR3 and DDR2 SDRAM devices. In Xilinx^® Vivado™, this core can be added as the DO-254 7 Series DDRx (Native-Limited) IP located in the DO-254 IP library with a Native Interface to DDR3 or DDR2 SDRAM architecture.

Key features are:

DDR3 SDRAM Features

Component support for interface widths up to 64 bits
DDR3 (1.5 V) and DDR3L (1.35 V)
1, 2, and 4 Gb density device support
8-bank support
x8 and x16 device support
8:1 DQ:DQS ratio support
Configurable data bus widths (multiples of 8, up to 72 bits)
8-word burst support
Support for 5 to 13 cycles of column-address strobe (CAS) latency (CL)
On-die termination (ODT) support (toggles the ODT signal during DDR3 R/W)
Support for 5 to 9 cycles of CAS write latency
Write leveling support for DDR3 (fly-by routing topology required for DDR3 component designs)
JEDEC-compliant DDR3 initialization support
Source code written in Verilog
4:1 and 2:1 memory to FPGA logic interface clock ratio
ECC support
I/O Power Reduction option average I/O power by automatically disabling DQ/DQS IBUFs and internal terminations during writes and periods of inactivity
Internal VREF support
Two controller request processing modes:
Normal: Reorder requests to optimize system throughput and latency
Strict: Memory requests are processed in the order received

DDR2 SDRAM Features

Component support for interface widths up to 64 bits (ECC is not available in DDR2 memories)
1 and 2 Gb density device support (additional densities supported in the MIG tool using the Create Custom Part feature)
4- and 8-bank support
x8 and x16 device support
8:1 DQ:DQS ratio support
Configurable data bus widths (multiples of 8, up to 64 bits)
8-word burst support
Support for 3 to 5 cycles of column address strobe (CAS) latency
On-die termination (ODT) support
JEDEC-compliant DDR2 initialization support
Source code written in Verilog
4:2 and 2:1 memory to FPGA logic interface clock ratio
I/O Power Reduction option reduces average I/O power by automatically disabling DQ/DQS IBUFs and internal terminations during writes and periods of inactivity
Internal VREF support
Two controller request processing modes:
- Normal: Reorder requests to optimize system throughput and latency
- Strict: Memory requests are processed in the order received

Documentation

The COTS version v1.07a is the baseline from which the DO-254 7-Series DDRx (Native-Limited) 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 7-Series DDRx (Native-Limited) 1.00a. Below are links to the Xilinx^® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx^® Product Specification:

https://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v1_8/ds176_7Series_MIS.pdf

Link to the Logicircuit Data Sheet:

DO-254 7-Series DDRx (Native-Limited) 1.00a Data Sheet