The Adder/Subtracter IP provides LUT and single Xtreme DSP™ slice add/sub implementations. The Adder/Subtracter module can implement adders (A+B), subtracters (A–B), and dynamically configurable adder/subtracters which operate on signed or unsigned data.
Key features are:
- Supports fabric implementation inputs ranging from 1 to 256 bits wide
- Supports Xtreme DSP slice implementation with inputs ranging from 1 to 36 or 48 bits wide (varies with device family selection)
- Optional carry input and output
- Latency configuration of manual or automatic for maximal speed performance
- Instantaneous Resource Estimation
- For use with Xilinx® CORE Generator™ , Xilinx® AccelDSP™ Synthesis Tool, and Xilinx® System Generator
Documentation
The COTS version v11.0 is the baseline from which the DO-254 Adder/Subtractor 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 Adder/Subtractor 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Specification:
http://www.xilinx.com/support/documentation/ip_documentation/addsub_ds214.pdf
Link to the Logicircuit Data Sheet:
DO-254 Adder/Subtractor 1.00a Data Sheet
Device Family Support
Xilinx® Artix™-7
Xilinx® Kintex™-7
Xilinx® Virtex™-7
Xilinx® Zynq™-7000
Xilinx® Spartan®-6
