DO-254 AXI Slave Burst 1.00a

The LogiCORE™ IP Advanced eXtensible Interface (AXI) Slave Burst is an interface between the AXI4 memory-mapped interface to the IPIC (IP Interconnect). This core is designed to provide a smooth migration path to the burst-supported IP from PLBv46 to AXI4 with minor updates in the interface. The core provides a point to point bi-directional interface between a user IP core and the AXI4 interconnect. This core acts as master on IPIC while it behaves as a slave on AXI4.

Key features are:

  • AXI4 Interface: 32 Bit Address bus, 32/64/128 Bit configurable data bus
  • IPIC Interface: 32 Bit Address bus, 32/64/128 Bit configurable data bus
  • Supports 1:1 (AXI4:IPIC) synchronous clock
  • Supports 1:1 (AXI4:IPIC) data width
  • AXI4 Interface
  • IPIC Interface



The COTS version v1.00a is the baseline from which the DO-254 AXI Slave Burst 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 AXI Slave Burst 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx® Product Specification:

Link to the Logicircuit Data Sheet:

DO-254 AXI Slave Burst 1.00a Data Sheet


Device Family Support

Xilinx® Artix™-7

Xilinx® Kintex™-7

Xilinx® Virtex™-7

Xilinx® Zynq™-7000

Xilinx® Spartan®-6