The UltraScale Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification. The core is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx® FPGAs. For SEU correction, the IP core performs the necessary operations to locate and correct SEU errors using the UltraScale built-in ECC facility. For SEU classification, the IP core uses Xilinx Essential Bits technology to further increase system reliability.
The UltraScale SEM IP core also performs emulation and monitoring of SEUs within Xilinx® UltraScale device by injecting errors into the configuration memory. The error injection feature provides a means to evaluate and test the readback CRC circuit and the error correction capabilities of the IP core.
Key features are:
- Typical detection latency of 13ms in many devices.
- Integration of built-in silicon primitives to fully leverage and improve upon the inherent error detection capability of the FPGA.
- Two modes
- Optional error correction based on error-correction code (ECC) algorithm with expedited correction time for multi-bit errors across adjacent frames.
- Using Xilinx® Essential Bits technology, optional error classification to determine if a soft error has affected the function of the user design.
- Increases uptime by avoiding disruptive recovery approaches for errors that have no effect on design operation
- Reduces effective failures-in-time (FIT)
- Optional error injection and convenient debug feature to support evaluation of SEM controller applications
- ICAP arbitration interface available to ease internal configuration access port (ICAP) primitive sharing
The COTS version v3.1 is the baseline from which the DO-254 UltraScale Soft Error Mitigation Controller 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 UltraScale Soft Error Mitigation Controller 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Guide:
UltraScale Architecture Soft Error Mitigation Controller v3.1
Link to the Logicircuit Data Sheet:
DO-254 UltraScale Soft Error Mitigation Controller 1.00a
ModelSim® v10.4c or later
Xilinx® Vivado® 2016.4 or later
Device Family Support
Xilinx® Kintex® UltraScale™ FPGA Family
Xilinx® Virtex® UltraScale™ FPGA Family