DO-254 AXI to PCI Bridge 1.00a

The DO-254 AXI to PCI Bridge 1.00a is an update to the older LogiCORE™ IP PLB46 PCI Full Bridge. The LogiCORE™ IP PLB46 PCI Full Bridge, created and designed by Xilinx®, provides full bridge functionality between the Xilinx® PLB and a 32-bit Revision 2.2 compliant Peripheral Component Interconnect (PCI™) bus. The Xilinx® PLB is a 32, 64, or 128-bit bus subset of the IBM PLB. The LogiCORE™ IP PCI32 core provides an interface with a standard 32-bit PCI bus.

The DO-254 AXI to PCI Bridge design provides full bridge functionality between the Xilinx® AXI interface and a 32-bit Revision 2.2 compliant Peripheral Component Interconnect (PCI™) bus. The LogiCORE™ IP PCI32 core provides an interface with the PCI bus. Host bridge functionality (often called North bridge functionality) is an optional functionality. Configuration Read and Write PCI commands can be performed from the AXI-side of the bridge. The DO-254 AXI to PCI Bridge supports a 32-bit/33 MHz PCI bus only.  The DO-254 AXI to PCI Bridge design has parameters that allow customers to configure the bridge to suit their application. The DO-254 AXI to PCI Bridge IP core allows bus communication via AXI and PCI interfaces to FPGAs.

Key features are:

  • Fully compatible 32-bit, 66/33 MHz Initiator/Target core for PCI™
  • Customizable, programmable, single-chip solution
  • Pre-defined implementation for predictable timing
  • Incorporates Xilinx® Smart-IP technology
  • 3.3V operation at 0–66 MHz
  • Fully verified design tested with Xilinx proprietary test bench and hardware
  • Delivered through the Xilinx® CORE Generator™ software
  • CardBus compliant
  • Supported initiator functions:
    •    Configuration read, configuration write
    •    Memory read, memory write, MRM, MRL User Guide v3
    •    Interrupt acknowledge, special cycles VHDL/Verilog Simulation Model
    •    I/O read, I/O write
  • Supported target functions:
    •    Type 0 configuration space header
    •    Up to three base address registers (MEM or I/O with adjustable block size from 16 bytes to 2   GB)
    •    Medium decode speed
    •    Parity generation, parity error detection
    •    Configuration read, configuration write
    •    Memory read, memory write, MRM, MRL
    •    Interrupt acknowledge
    •    I/O read, I/O write
    •    Target abort, target retry, target disconnect

 

Documentation

The DO-254 AXI to PCI Bridge 1.00a was created by Logicircuit. This design utilized the COTS version v1.04.a for the PCI portion of the IP. Logicircuit designed the Bridge. Below are links to the Xilinx® Product Data for the version that was used as a guide, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx® Product Specification:

http://www.xilinx.com/support/documentation/ip_documentation/pci32/v4_15/pci_32_ds206.pdf

Llink to the Logicircuit Data Sheet:

DO-254 AXI to PCI Bridge 1.00a Data Sheet

 

Device Family Support

Xilinx® Artix™-7

Xilinx® Kintex™-7

Xilinx® Virtex™-7

Xilinx® Zynq™-7000

Xilinx® Spartan®-6