The AXI Serial Peripheral Interface (SPI) connects to the Advanced eXtensible Interface (AXI4). This core provides a serial interface to SPI devices such as SPI EEPROMs and SPI serial flash devices. The SPI protocol, as described in the Motorola M68HC11 data sheet, provides a simple method for a master and a selected slave to exchange data. This 32-bit soft IP core is designed to interface with the AXI4-Lite interface.
Key Features are:
- AXI4-Lite interface is based on the AXI4 specification
- Connects as a 32-bit AXI4-Lite slave
- Supports four signal interface (MOSI, MISO, SCK and SS)
- Supports slave select (SS) bit for each slave on the SPI bus
- Supports full-duplex operation
- Supports master and slave SPI modes
- Supports programmable clock phase and polarity
- Supports continuous transfer mode for automatic scanning of a peripheral
Documentation
The COTS version v1.02.a is the baseline from which the DO-254 AXI Serial Peripheral Interface (SPI) 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 AXI Serial Peripheral Interface (SPI) 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Specification:
http://www.xilinx.com/support/documentation/ip_documentation/axi_spi/v1_02_a/axi_spi_ds742.pdf
Link to the Logicircuit Data Sheet:
DO-254 AXI Serial Peripheral Interface (SPI) 1.00a Data Sheet
Device Family Support
Xilinx® Artix™-7
Xilinx® Kintex™-7
Xilinx® Virtex™-7
Xilinx® Zynq™-7000
Xilinx® Spartan®-6
