DO-254 AXI Bridge for PCI Express (PCIe) Limited 1.00a

The AXI Bridge for PCI Express® (PCIe) IP core provides an interface between an AXI4 customer user interface and PCI Express using the Xilinx® Integrated Block for PCI Express. The core provides the translation level between the AXI4 embedded system to the PCI Express system in Xilinx® FPGAs.

Key features are:

  • AXI Bridge for PCIe Gen2 supports Maximum Payload Size (MPS) up to 256 bytes
  • Multiple Vector Messaged Signaled Interrupts (MSIs) capability of the FPGA
  • Legacy interrupt support
  • Memory-mapped AXI4 access to PCIe® space
  • PCIe access to memory-mapped AXI4 space
  • Tracks and manages Transaction Layer Packets (TLPs) completion processing
  • Detects and indicates error conditions with interrupts
  • Optimal AXI4 pipeline support for enhanced performance
  • Supports a single PCIe 32-bit BAR as Root Port



The COTS version v2.8 is the baseline from which the DO-254 AXI Bridge for PCI Express® (PCIe) 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 AXI Bridge for PCI Express® (PCIe) 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx® Product Guide:

Link to the Logicircuit Data Sheet:

<Unavailable at the moment>


ModelSim® v10.4c or later

Xilinx® Vivado® 2019.1 or later


Device Family Support

Xilinx® Artix™-7

Xilinx® Kintex™-7

Xilinx® Virtex™-7

Xilinx® Zynq™-7