The Advanced eXtensible Interface (AXI) Master Burst is a continuation of the Xilinx family of AXI4-compatible LogiCORE™ IP products. It provides a bidirectional interface between a user IP core and the AXI4 interface standard. This version of the AXI Master Burst has been optimized for bus mastering operations consisting of burst transactions.
Key features are:
- Compatible with 32, 64, and 128-bit AXI4
- Parameterizable data width of Client IP Interface (IPIC) to 32, 64, or 128-bits
- Supports AXI4 read and write data burts of 16, 32, 64, 128, and 256 maximum data beats
- Transfer width is equal to the parameterized IPIC data width
- Automatic AXI4 4K byte address boundary crossing protection
- The User interface consists of a Legacy Command/Status interface and read and write LocalLink interfaces for the data transactions
Documentation
The COTS version v1.00.a is the baseline from which the DO-254 AXI Master Burst 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 AXI Master Burst 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Specification:
Link to the Logicircuit Data Sheet:
DO-254 AXI Master Burst 1.00a Data Sheet
Device Family Support
Xilinx® Artix™-7
Xilinx® Kintex™-7
Xilinx® Virtex™-7
Xilinx® Zynq™-7000
Xilinx® Spartan®-6
