DO-254 DDR Memory Controller 1.00a

The MCB is a dedicated embedded block multi-port memory controller that greatly simplifies the task of interfacing Spartan-6 devices to the most popular memory standards. The MCB provides significantly higher performance, reduced power consumption, and faster development times than equivalent IP implementations. The embedded block implementation of the MCB conserves valuable FPGA resources and allows the user to focus on the more unique features of the FPGA design.

Key features are:

  • DDR, DDR2, DDR3, and LPDDR (Mobile DDR) memory standards support
  • Up to 800 Mb/s (400 MHz double data rate) performance
  • Up to four MCB cores in a single Spartan-6 device
  • Configurable dedicated multi-port user interface to FPGA logic
  • Memory Bank Management
  • Embedded controller and physical interface (PHY)
  • Predefined pinouts (I/O locations) for each MCB
  • Common memory device options and attributes support
  • Automatic delay calibration of memory strobe and read data inputs
  • Optional automatic calibration of FPGA on-chip input termination for optimal signal integrity
  • Supported by Xilinx® CORE Generator™ and Embedded Development Kit (EDK) design tools



The COTS version v2.3 is the baseline from which the DO-254 DDR Memory Controller 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 DDR Memory Controller 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx® User Guide:

Link to the Logicircuit Data sheet:

DO-254 DDR Memory Controller 1.00a Data Sheet


Device Family Support

Xilinx® Spartan®-6