DO-254 Fast Simplex Link (FSL) 1.00a

The LogiCORE™ IP FSL V20 Fast Simplex Link (FSL) Bus is
a uni-directional point-to-point communication channel bus used to perform fast
communication between any two design elements on the FPGA when implementing an
interface to the DO-254 FSL bus.  The DO-254 FSL interface is available on the Xilinx® MicroBlaze™ processor.  The interfaces are used to transfer data to and from the register file on the
processor to hardware running on the FPGA.

Key features are:

  • Implements a uni-directional point to point FIFO-based communication
  • Provides a mechanism for unshared and non-arbitrated communication.  This can be used for fast transfer of data words between a mster and a slave, thus implementing the FSL interface.
  • Provides an extra control bit for annotating transmit data.  This bit can be used by the slave-side interface for different purposes, such as decoding the transmit word as a control word, or using the bit to indicate the start or end of frame transmission.
  • FIFO depths can be as low as 1K and as high as 8K.
  • Supports synchronous and asynchronous FIFO modes.  This allows the maste and slave side of the FSL to clock at different rates.
  • Support for SRL16 and dual port LUT RAM or block RAM based FIFO implementation.



The COTS version v2.11e is the baseline from which the DO-254 Fast Simplex Link (FSL) 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 Fast Simplex Link (FSL) 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx® Product Specification:

Link to the Logicircuit Data Sheet:

DO-254 FSL 1.00a Data Sheet


Device Family Support

Xilinx® Artix™-7

Xilinx® Kintex™-7

Xilinx® Virtex™-7

Xilinx® Zynq™-7000

Xilinx® Spartan®-6