The Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller is a module that attaches to one LMB. It supports the LMB bus protocol and byte enable architecture. Any access size up to the width of the LMB data bus is permitted. The LMB BRAM Interface Controller is the interface between the LMB and the BRAM block peripheral. A BRAM memory subsystem consists of the controller along with the actual BRAM components that are included in the BRAM block peripheral.
Key features are:
- LMB v1.0 bus interfaces with byte enable support
- Used in conjunction with BRAM block peripheral to provide fast BRAM memory solution for MicroBlaze™ ILMB and DLMB ports
- Supports byte, half-word, and word transfers
Documentation
The COTS version v3.00.b is the baseline from which the DO-254 Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Specification:
Link to the Logicircuit Data Sheet:
DO-254 Local Memory Bus (LMB) Block RAM (BRAM) Interface Controller 1.00a Data Sheet
Device Family Support
Xilinx® Artix™-7
Xilinx® Kintex™-7
Xilinx® Virtex™-7
Xilinx® Zynq™-7000
Xilinx® Spartan®-6
