The multiplier operation is essential and abundant in DSP applications. Achieving maximum implementation efficiency and clock performance is therefore critical to DSP systems and frequently presents a significant challenge to hardware engineers.
The LogiCORE™ Multiplier simplifies this challenge by abstracting away FPGA device specifics, while maintaining the required maximum performance and resource efficiency. The multiplier is able to generate parallel multipliers, and constant coefficient multipliers, both with differing implementation styles. Furthermore, with the aid of instantaneous resource estimation, hardware engineers can rapidly select the optimal solution for their system.
The latest additions to the IP provide fine control over the latency (pipelining) of the multipliers (purely combinatorial to fully pipelined) and symmetric rounding on XtremeDSPTM slice based multiplication under 18 bits. Finally, fully pipelined implementations enable maximum clock frequency performance of 450 MHz and 250 MHz when DSP48 components are used in Virtex™-6 (-1) and Spartan®-6 (-2) respectively.
Key features are:
- LUT based speed and area optimized implementation for Virtex™-5, Virtex™-6 and Spartan®-6
- 2’s complement signed/unsigned fixed point multiplier
- Parallel and fixed constant coefficient multipliers
- Input data width from 2-64 bits
- Variable levels of pipelining
- Symmetric Rounding for up to 18 bit XtremeDSP Slice based multipliers
- Supports three different types of multiplier construction for Virtex™-4/5 and Spartan-3A DSP Platforms: Use LUTs, Use DSP48/E and Hybrid implementation (for larger than 18-bit multipliers)
- Supports three different types of multiplier construction for Virtex™-II/Spartan®-3 families: Use LUTs, Use Embedded Multipliers and Hybrid implementation (for larger than 18 bit multipliers)
- Instantaneous Resource Estimation
- Optional Clock Enable, and Synchronous Clear
- VHDL behavioral models
- Instantaneous Resource Estimation
- For use with Xilinx® CORE Generator™ , Xilinx® AccelDSP™ Synthesis Tool, and Xilinx® System Generator
Documentation
The COTS version v11.2 is the baseline from which the DO-254 Multiplier 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 Multiplier 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Specification:
http://www.xilinx.com/support/documentation/ip_documentation/mult_gen_ds255.pdf
Link to the Logicircuit Data Sheet:
DO-254 Multiplier 1.00a Data Sheet
Family Device Support
Xilinx® Artix™-7
Xilinx® Kintex™-7
Xilinx® Virtex™-7
Xilinx® Zynq™-7000
Xilinx® Spartan®-6
