The Processor System Reset Module design allows the customer to tailor the design to suit their application by setting certain parameters to enable/disable features.
Key features are:
- Asynchronous external reset input is synchronized with clock
- Asynchronous auxiliary external reset input is synchronized with clock
- Both the external and auxiliary reset inputs are selectable active high or active low
- Selectable minimum pulse width for reset inputs to be recognized
- Selectable load equalizing
- DCM Locked input
- Power On Reset generation
Documentation
The COTS version v3.00a is the baseline from which the DO-254 Processor System Reset Module 1.02a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 Processor System Reset Module 1.02a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Specification:
http://www.xilinx.com/support/documentation/ip_documentation/proc_sys_reset.pdf
Link to the Logicircuit Data Sheet:
DO-254 Processor System Reset Module 1.02a Data Sheet
Core Configurations
| Core Version | Tool Capability |
| 1.00a | Xilinx® ISE/EDK® 13.4
ModelSim® v10.1c Xilinx® ISIM 13.4 or later Xilinx® XST 13.4 or later |
| 1.01a | Xilinx® ISE/EDK® 14.4
ModelSim® v10.1c Xilinx® ISIM 14.4 or later Xilinx® XST 14.4 or later Xilinx® Vivado® 2016.1 or later |
| 1.02a | Xilinx® ISE/EDK® 14.4
ModelSim® v10.1c Xilinx® ISIM 14.4 or later Xilinx® XST 14.4 or later Xilinx® Vivado® 2016.1 or later |
Tools
Xilinx® EDK® 14.4 or later
ModelSim® v10.1c or later
Xilinx® ISIM 14.4 or later
Xilinx® XST 14.4 or later
Xilinx® Vivado® 2016.1 or later
Device Family Support
Xilinx® Artix™-7
Xilinx® Kintex™-7
Xilinx® Virtex™-7
Xilinx® Zynq™-7000
Xilinx® Spartan®-6
