The UltraScale+ Soft Error Mitigation (SEM) IP core performs SEU detection, correction, and classification. The core is an automatically configured, pre-verified solution to detect and correct soft errors in Configuration Memory of Xilinx® FPGAs. For SEU correction, the IP core performs the necessary operations to locate and correct SEU errors using the UltraScale built-in ECC facility. For SEU classification, the IP core uses Xilinx Essential Bits technology to further increase system reliability.
The UltraScale+ SEM IP core also performs emulation and monitoring of SEUs within Xilinx® UltraScale device by injecting errors into the configuration memory. The error injection feature provides a means to evaluate and test the readback CRC circuit and the error correction capabilities of the IP core.
Key features are:
- Typical detection latency of 25ms in many devices
- Integration of built-in silicon primitives to fully leverage and improve upon the inherent error detection capability of the FPGA
- Six modes
- Mitigation and Testing
- Mitigation only
- Detect and Testing
- Detect only
- Optional error correction, using selectable method: repair, enhanced repair, or replace
- Correction by repair method is ECC algorithm based
- Correction by enhanced repair method is ECC and CRC algorithm based
- Correction by replace method is data re-load based
- Using Xilinx® Essential Bits technology, optional error classification to determine if a soft error has affected the function of the user design
- Increases uptime by avoiding disruptive recovery approaches for errors that have no effect on design operation
- Reduces effective failures-in-time (FIT)
- Optional error injection to support evaluation of UltraScale+ Soft Error Mitigation Controller applications
Other DO-254 UltraScale+ Soft Error Mitigation Controller features include:
- Integration of silicon features to leverage built-in error detection capability
- Implementation of error correction capability to support correction of soft errors. The error correction method can be defined as:
- Repair – ECC algorithm-based correction. This method supports correction of configuration memory frames with single-bit errors. This covers correction of all single-bit upset events. It also covers correction of multi-bit upset events when errors are distributed one per frame as a result of configuration memory interleaving.
- Enhanced Repair – ECC and CRC algorithm-based correction. This method supports correction of configuration memory frames with single-bit errors or double-bit adjacent errors. This covers correction of all single-bit upset events and all double-bit adjacent upset events. This also covers correction of multi-bit upset events when errors are distributed one or two adjacent per frame as a result of configuration memory interleaving.
- Replace – Data reload based correction. This method supports correction of configuration memory frames with arbitrary errors. This covers correction of any upset event that can be resolved to specific configuration memory frames; even if the exact bit locations in the frames cannot be determined.
- Implementation of error classification capability to determine if corrected errors have affected configuration memory in locations essential to the function of the design
- Provision for error injection to support verification of the controller and evaluation of applications to the controller
The COTS version v3.1 is the baseline from which the DO-254 UltraScale+ Soft Error Mitigation Controller 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 UltraScale+ Soft Error Mitigation Controller 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Guide:
Link to the Logicircuit Data Sheet:
QuestaSim® v10.4 or later
Xilinx® Vivado® 2019.1 or later
Device Family Support
Xilinx® Kintex® UltraScale+™ FPGA Family
Xilinx® Virtex® UltraScale+™ FPGA Family
Xilinx® Zynq® UltraScale+™ FPGA Family