The Distributed Memory Generator IP core creates a variety of memory structures using Select RAM. It can be used to create Read Only Memory (ROM), single-port Random Access Memory (RAM), and simple dual/Dual port RAM as well as SRL16-based RAM. Flexible feature set allows users to customize for Memory type, Data width, Memory size, Input/Output options and reset options.
Key features are:
- Generates Read Only Memories (ROMs), Single, Simple Dual and Dual-port Random Access Memories (RAMs), and SRL16-based RAMs
- Supports data depths ranging from 16 to 65,536 words
- Supports data widths ranging from 1 to 1024 bits
- Optional registered inputs and outputs
- Example Design helps you get up and running quickly
Documentation
The COTS version v7.2 is the baseline from which the DO-254 Distributed Memory Generator 1.00a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 Distributed Memory Generator 1.00a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.
Link to the Xilinx® Product Guide:
Link to the Logicircuit Data Sheet:
DO-254 Distributed Memory Generator Data Sheet 1.00a
Device Family Support
Xilinx® Artix™-7
Xilinx® Kintex™-7
Xilinx® Virtex™-7
Xilinx® Zynq™-7000
Xilinx® Spartan®-6
