DO-254 Floating Point Operator (Limited) 1.10a

The Floating Point Operator IP core provides the user with the means to perform floating point arithmetic on Xilinx® Field Programmable Gate Arrays (FPGAs). The operation is specified when the core is generated, and each operation variant has a common interface. The DO-254 Floating Point Operator allows converts from floating point to fixed point and fixed point to floating point.

Key features are:

  • Supports the following operators:
    • Multiply
    • Divide
    • Add
    • Conversion from floating-point to fixed-point
    • Conversion from fixed-point to floating-point
    • Comparison (greater than and less than)
  • Compliance with IEEE-754 Standard
  • Parameterized fraction and exponent wordlengths for most operators
  • Optimized for speed
  • Fully synchronous design using a single clock

Documentation

The COTS version v7.0 is the baseline from which the DO-254 Floating Point Operator 1.10a comes from. Logicircuit applies the DO-254 lifecycle to this COTS version. As a result of this DO-254 process, the source code will be modified with the goal of achieving 100% code coverage, and the resulting code will be named DO-254 Floating Point Operator 1.10a. Below are links to the Xilinx® Product Data for the version that was used as the basis, and the Logicircuit Data Sheet of the resulting DO-254 product.

Link to the Xilinx® Product Guide:

https://www.xilinx.com/support/documentation/ip_documentation/floating_point/v7_0/pg060-floating-point.pdf

Link to the Logicircuit Data Sheet:

DO-254 Floating Point Operator v1.10a

Core Configurations

Core Version Features Tool Capability
1.00a
  • Supports the following operators:
    • Multiply
    • Divide
    • Add
    • Conversion from floating-point to fixed-point
    • Conversion from fixed-point to floating-point
    • Comparison (greater than and less than)
  • Compliance with IEEE-754 Standard
  • Parameterized fraction and exponent wordlengths for most operators
  • Optimized for speed
  • Fully synchronous design using a single clock
ModelSim® v10.4 or later

Xilinx® Vivado® 2016.1 or later

1.10a
  • Supports the following operators:
    • Multiply
    • Divide
    • Add
    • Square Root
    • Conversion from floating-point to fixed-point
    • Conversion from fixed-point to floating-point
    • Comparison (greater than and less than)
  • Compliance with IEEE-754 Standard
  • Parameterized fraction and exponent wordlengths for most operators
  • Optimized for speed

Fully synchronous design using a single clock

ModelSim® v10.4 or later

Xilinx® Vivado® 2016.1 or later

Tools

ModelSim® v10.4 or later

Xilinx® Vivado® 2016.1 or later

Device Family Support

Xilinx® Artix™-7

Xilinx® Kintex™-7

Xilinx® Virtex™-7

Xilinx® Zynq™-7

Xilinx® Artix® UltraScale™ FPGA Family

Xilinx® Kintex® UltraScale™ FPGA Family

Xilinx® Virtex® UltraScale™ FPGA Family

Xilinx® Zynq® UltraScale™ FPGA Family